The present invention relates to stacked microelectronic assemblies and methods of making such assemblies, and to components useful in such assemblies.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a front surface having contacts connected to the active circuitry of the chip. Each individual chip typically is mounted in a package which, in turn, is mounted on a circuit panel such as a printed circuit board and which connects the contacts of the chip to conductors of the circuit panel. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure with reference to a flat chip having a front surface, the “area of the chip” should be understood as referring to the area of the front surface.
In “flip chip” designs, the front surface of the chip confronts a surface of a package substrate, i.e., a chip carrier, and the contacts on the chip are bonded directly to contacts of the chip carrier by solder balls or other connecting elements. In turn, the chip carrier can be bonded to a circuit panel through terminals overlying the front surface of the chip. The “flip chip” design provides a relatively compact arrangement; each chip occupies an area of the circuit panel equal to or slightly larger than the area of the chip's front surface, such as disclosed, for example, in certain embodiments of commonly-assigned U.S. Pat. Nos. 5,148,265, 5,148,266, and 5,679,977, the disclosures of which are incorporated herein by reference.
Besides minimizing the planar area of the circuit panel occupied by microelectronic assembly, it is also desirable to produce a chip package that presents a low overall height or dimension perpendicular to the plane of the circuit panel. Such thin microelectronic packages allow for placement of a circuit panel having the packages mounted therein in close proximity to neighboring structures, thus reducing the overall size of the product incorporating the circuit panel.
It has also been proposed to package plural chips in a “stacked” arrangement, i.e., an arrangement where plural chips are placed one on top of another. In a stacked arrangement, several chips can be mounted in an area of the circuit panel that is less than the total area of the chips. Certain stacked chip arrangements are disclosed, for example, in certain embodiments of the aforementioned U.S. Pat. Nos. 5,148,265, 5,679,977, and U.S. Pat. No. 5,347,159, the disclosure of which is incorporated herein by reference. U.S. Pat. No. 4,941,033, also incorporated herein by reference, discloses an arrangement in which chips are stacked on top of another and interconnected with one another by conductors on so-called “wiring films” associated with the chips.
Conventional chip contacts may have reliability challenges because of a non-optimal stress distribution at the contact and a mismatch of the coefficient of thermal expansion (CTE) between a semiconductor chip, for example, and the structure to which the chip is bonded. For example, when conductive contacts at a surface of a semiconductor chip are insulated by a relatively thin and stiff dielectric material, significant stresses may be present at the contacts. In addition, when the semiconductor chip is bonded to conductive elements of a polymeric substrate, the electrical connections between the chip and the higher CTE structure of the substrate will be under stress due to CTE mismatch.
Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/O's.” These I/O's must be interconnected with the I/O's of other chips. The interconnections should be short and should have low impedance to minimize signal propagation delays. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines. For example, structures which provide numerous short, low-impedance interconnects between complex chips can increase the bandwidth of the search engine and reduce its power consumption.
Despite the advances that have been made in semiconductor contact formation and interconnection, there is still a need for improvements in order to minimize the size of semiconductor chips, while enhancing electrical interconnection reliability. These attributes of the present invention are achieved by the construction of the microelectronic packages as described hereinafter.